This invention is in the field of solid-state integrated circuits. Embodiments of this invention are directed to computer-implemented tools for designing the layout of such integrated circuits.
Advances in semiconductor technology in recent years have enabled the shrinking of minimum device feature sizes, such as metal-oxide-semiconductor (MOS) transistor gates, into the deep sub-micron range. For example, according to some advanced manufacturing technologies as of this date, the target MOS transistor gate width after etch is on the order of 30 nm. This continuing trend toward smaller device sizes, in combination with continuing improvement in manufacturing technology, have enabled the functionality of very large-scale integrated circuits to greatly increase. A single modern integrated circuit can now contain over one billion transistors, with that number expected to continue to increase as still-smaller technology “nodes” become manufacturable. The ability to realize so many active devices in a single integrated circuit has, of course, resulted in the integration of complex functionality into that integrated circuit, including computing resources operating on very wide data words (e.g., sixty-four bits or wider).
As the number of transistors embodied in a single integrated circuit has increased to such levels, the task of designing the integrated circuit to attain the resulting functional complexity has also become quite complex. Also involved in the implementation of such functionality into an integrated circuit is the task of defining the physical position and physical attributes of each active device, passive device, and interconnection among those devices, to such an extent that photomasks can be created to define those elements in each of the various material layers to be involved in the physical construction of the integrated circuit. As known in the art, this task is referred to as “layout”.
A conventional approach to facilitating the design and layout of very large scale integrated circuits, particularly such an integrated circuit that is to carry out a specific function (e.g., a particular computational or control function desired by a system manufacturer), is referred to as the “ASIC” (“Application-Specific Integrated Circuit”) design flow. According to this approach, the integrated circuit layout appears as multiple previously-designed and laid-out circuit blocks (i.e., standard cells) for specific functions, memories, and input/output cells arranged in a somewhat regular grid within the rectangular boundaries of the integrated circuit. Interconnections among the various standard cells, I/O blocks, and memories reside in overlying conductor layers.
As known in the art, the ASIC design flow now typically uses commercially-available design tools to convert a system specification into a data file (e.g., the “pattern generation” or “PG” file) from which photomasks can be constructed for manufacture of the integrated circuit. FIG. 1a is a somewhat simplified high-level flow diagram illustrating a typical conventional ASIC design flow. In process 10, the system specifications are defined by the design team. These specifications of course include the desired functionality and performance of the integrated circuit, as well as any constraints (e.g., maximum chip area, power dissipation). In addition, process 10 identifies the manufacturing technology to be used in the manufacture of the integrated circuit (e.g., twin-well CMOS), including the minimum device sizes available for the technology. The specifications defined in process 10 also include functional and architectural specifications, such as the class of instruction set to be implemented (e.g., RISC or CISC), functional features such as pipelining and the number of “cores” for processing units in the integrated circuit. Typical functional and architectural specifications for modern ASICs also break down the overall functionality into various subchips, and identify the relationship between those subchips and the overall, “top-level”, system.
These system specifications defined in process 10 serve as the input for logic design process 12. This process 12 implements the system specification into a logic representation of the integrated circuit, for example at a level including sequential or combinatorial logic, Boolean expressions, registers, and the like. This logic representation is typically expressed in a “hardware description language” (“HDL”), as known in the art. Verification that the resulting HDL expression of the integrated circuit corresponds to the higher-level system specifications is typically performed.
In this high-level ASIC flow, the HDL expression of the integrated circuit is then converted into a “gate level netlist” by way of logic synthesis process 14. Conventional synthesis tools are available in the industry to assist the design team in carrying out synthesis process 14. As known in the art, these synthesis tools receive the HDL representation, along with the desired library of “standard cells” available for use in the design, and creates a list of the interconnections, at the gate level, between the various logic functions in the device. Cost constraints are generally applied in synthesis process 14, so that an optimal netlist for a particular manufacturing technology and process can be selected. Typically, in a standard cell ASIC design, the netlist is a complete structural description of the integrated circuit, with each “net” referring to an interconnection among two or more standard cell nodes (or an input/output pad). Simulation can be applied to this structural description, to verify the logic design and perhaps to confirm high level performance.
Physical implementation process 16 turns the netlist and standard cells from process 14 into a geometric representation of the physical layout of the integrated circuit. The desired result of physical implementation process 16 is a data file (PG file) from which photomasks can be generated for use in defining physical features in the various layers of the selected manufacturing technology, in the manufacture of integrated circuits in process 16.
FIG. 1b illustrates a typical flow for carrying out physical implementation process 16, according to conventional approaches. In a general sense, physical implementation process 16 begins with “floorplanning” the integrated circuit (process 13). Floorplanning process 13 defines the high level arrangement of the physical integrated circuit, including identification of the width and length of the eventual integrated circuit. Modern ASIC layouts arrange the subchips (i.e., standard cells, memory blocks, and I/O functions) according to a gridded (“Manhattan”) approach. The routing of power supply voltages is also defined in the floorplanning stage, since each subchip will require at least one power supply voltage and a corresponding ground or reference voltage. The location of input/output blocks and external connections “pads” can also be selected in floorplanning process 13. In placement process 15, the locations of the subchips in the floorplan defined in process 13 are selected. Circuit macros and logic gates within each of those subchips are also arranged and located within the physical floorplan as part of placement process 15.
Following placement process 15 (and any verification desired by the design team), routing process 17 is then carried out to define the geometric placement of interconnections between the subchips as placed in process 13, and of course based on the netlist from logic synthesis process 14. According to conventional ASIC layout techniques, a grid of horizontal and vertical “wiring tracks” overlays the layout of the integrated circuit. As mentioned above, the power and ground buses are assigned to specific tracks, creating power and ground “meshes” in this overlay. The remaining tracks can be used for interconnects between subchips. In this grid arrangement, interconnects are generally constrained to running either in a horizontal or vertical directions along tracks. Typically, one conductor layer is dedicated to horizontal interconnect segments, and another, adjacent, conductor layer is dedicated to vertical interconnect segments; for example, even-numbered conductor layers (e.g., “the metal 2 level”) may be dedicated to horizontal interconnect segments in the x-y plane, with odd-numbered conductor layers (e.g., “the metal 3 level”) dedicated to vertical segments in that plane. Vias through the intervening insulator layers form connections among the various conductor layers.
Interconnects in an integrated circuit design can be routed manually, typically by a design engineer interactively selecting the routing path for each interconnect in the layout. Manual routing can provide a highly regular pattern of interconnects, with optimal utilization of wiring tracks and routing resources. However, manual routing is a prohibitively time-consuming, expensive, and error-prone task for modern complex integrated circuits, especially those with many subchips and input/output resources, and ultra-wide data word widths. The difficulties of manual routing are exacerbated as the integrated circuit becomes relatively large in chip area, because the routing of long on-chip interconnect distances, the large number of geometries, and the necessarily-occurring irregularities in such large devices complicate the routing problem. Worse yet, a small change in a routing path, or an interconnect line width, can result in a “domino effect”, necessitating changes in hundreds of other interconnects beginning with near neighbors. Manual routing has therefore become essentially impractical for integrated circuits of moderate and higher complexity.
At the other end of the spectrum, automated router software packages (“autorouters”) are available for carrying out routing process 17 with greatly improved efficiency relative to manual routing. Autorouter tools operate by deriving an interconnect routing that reflects the netlist of the circuit, as applied to the result of placement process 15. However, it has been observed that wiring derived by such automated routing tools typically appears somewhat random, with little regularity exhibited in the interconnect paths. For example, autorouted integrated circuits typically do not include data bus structures, in which parallel interconnects for multiple bits in a data word run largely in parallel between their endpoints. Rather, the individual wires in potential data buses can follow paths that are largely independent of one another. In addition, it has been observed that autorouters tend to under-utilize the available wiring tracks as compared with manual routing efforts. In the worst case, designs having a significant amount of “top-level” wiring, in the form of wide data buses that heavily utilize the available metal resources, often result in the autorouter not converging to a routing solution.
Some design engineers use a combination of manual routing and autorouting to arrive at the layout of interconnections. For example, the design engineer may manually route some of the interconnections, and allow the autorouter to make the rest of the connections, constrained by the manually routed paths. This combination can attain good area efficiency and regularity in many of the interconnections, while avoiding the painstaking routing involved with the remaining more random wires.
By way of further background, my copending and commonly assigned U.S. application Ser. No. 13/297,086 entitled “An Interactive Routing Editor with Symbolic and Geometric Views for Integrated Circuit Layout”, filed Nov. 15, 2011 and incorporated herein by reference, describes an automated system and method for interactively routing interconnections in a layout of an integrated circuit. Top level interconnections among subchips in the integrated circuit, specified by a netlist, and that are arranged as a bus, are displayed in a symbolic view by a representative wire of the bus, for example the least-significant or most-significant bit position in the bus. The physical routing of the representative wire is interactively defined, using orthogonal wire segments of the representative wire in selected conductor levels. Bus properties, for example including bit pitch, wire pitch, LSB/MSB (when displayed in the symbolic view), and a direction of expansion, are associated with the routing data for each segment of the representative wire. By combining the routing data and the bus property data, the system can build the entire bus for display in a geometric view.
As known in the art, it is common for the floorplan of an integrated circuit layout to change, for any one of a number of reasons, at a late stage in the design process. Examples of these floorplan changes include changes in the arrangement or size of one or more toplevel blocks (i.e., subchips), relatively small adjustments to the position of blocks (such as to accommodate size or shape changes of the adjusted blocks themselves, or of neighboring blocks), adjustments to the spacing between blocks, up to wholesale rearrangement of blocks in the floorplan. Such changes in the floorplan after the interconnections have been partially or fully routed will of course require changes in the affected wiring.
In conventional design systems, re-routing of toplevel interconnections following a change in the floorplan is typically performed manually. Even for small floorplan changes, the time and effort required for updating the routing can be significant, and in some cases can consume as much manpower and time as the original routing. Floorplan changes occurring late in the layout process can of course be especially costly in design time and the product development schedule. This extreme cost of re-routing can, in some cases, necessitate “freezing” the layout, foregoing the potential benefit in performance or chip area that may have been available if the floorplan could have been adjusted.